This U.S. patent application is related to U.S. patent applications filed herewith, and identified as Attorney Docket Numbers 01-C-041 and 01-C-043.
The present invention relates in general to semiconductor devices and processing methods, and more particularly to the use of an organic polymer protective coating on semiconductor chips having surfaces exposed to the environment.
Integrated circuits are employed in many different environments which require protection against mechanical damage, chemical deterioration, electromagnetic and electrostatic invasion, and a host of other agents. Conventional integrated circuits are fabricated on wafers, each of which consists primarily of a monocrystalline silicon substrate. Upon completion of the fabrication process, the wafer is sliced into separate square or rectangular chips, each including a complete integrated circuit, which is then encapsulated to form a finished device.
The manner in which an integrated circuit is fabricated and packaged determines in a large part how well the chip is protected from the foregoing environmental effects. The outer package of an integrated chip is intended to provide mechanical protection, and to a certain degree moisture protection. The integrated chip itself is fabricated with various passivation layers to provide intimate protection from numerous environmental attacks, including ion diffusion (sodium ions especially) into the active circuitry of the semiconductor chip. An industry standard for passivation of a semiconductor chip is to deposit an inorganic silicon nitride material over the surface of the chip. This passivation material provides an excellent barrier and protects the active circuitry from the adverse effects of moisture, sodium and other similar ions.
Integrated circuits have traditionally been packaged with a plastic, ceramic or other type of encapsulating material to provide mechanical and moisture protection to the chip. The pins or contact pads of the packaged chip are accessible to provide electrical access to the circuits of the chip. This is a common packaging technique, as the only access required to the chip is by way of electrical signals.
A new generation of integrated circuit chips has evolved where a mechanical or physical input to the chip is necessary. One such type of integrated circuit is used in the biometric field where a physical input, such as a finger touch to the chip, is used so that corresponding signals can be processed by the chip to produce an output related to the touch. In one family of integrated chips, a surface or physical interface of the chip is not encased or encapsulated in the conventional manner, but rather is accessible for touching by a fingertip so the image of a fingerprint can be electrically generated by the circuits of the chip. An array of sensing capacitors is fabricated near the exposed surface of the chip to sense the ridges and valleys of the fingerprint. Such type of integrated circuit is disclosed in U.S. Pat. No. 6,114,862 by Tartagni, et. al., assigned to the assignee hereof. Other sensing techniques are available in integrated circuits for reproducing a person""s fingerprint when the integrated circuit is touched.
When a physical interface is necessary between the integrated circuit chip and the environment, special precautions must be taken, as the use of conventional encapsulation is often not an option. The physical interface must not interfere with the interaction between the environment and the chip, whether it be the texture of an object such as a fingerprint, the temperature of the article physically contacting the chip interface, optical inputs, etc. When an integrated circuit chip is provided with a physical interface exposed to the environment, there is always a concern that such an interface is sufficiently rugged, but yet also sufficiently protective to the underlying circuits. Conventionally, the physical interface to biometric fingerprint sensors involves the use of a very thin silicon carbide layer covering a silicon nitride passivation layer. Silicon carbide is well known for its durability, in that it is an extremely hard material. When used with capacitor-type fingerprint sensors, the thickness of the passivation layer and the physical protective layer should be relatively thin so as not to compromise the sensitivity of the sensing circuits to the differences in the physical properties that exist between the ridges (flesh) and valleys (air gaps) of the fingerprint. It has been found that when a thin silicon carbide layer is used for the physical interface, it is very durable and highly wear resistant, but can nevertheless crack or break when subjected to concentrated loads. Although the silicon carbide material provides an extremely hard physical interface, the brittle characteristic of such material is a disadvantage, especially when it is subjected to impact forces produced by sharp or pointed objects.
FIG. 1 illustrates the material layers of a conventional semiconductor chip of the type that has a physical interface to the environment. In this type of integrated circuit, a metal layer 10 forming a network is deposited on an intermediate layer, and patterned, so as to form a matrix of fringing capacitors to sense the ridges and valleys of a fingerprint. The principle of operation of such type of integrated circuit is set forth in more detail in U.S. Pat. No. 6,114,862, noted above. The basic structure includes two side-by-side capacitor plates at each sensor cell or pixel of an array of such pixels. The skin surface of the user""s finger, when pressed against the sensing surface or physical interface, forms a common capacitor plate with the side-by-side plates at each pixel and effectively modulates the fringing capacitance between the plates. The change in the fringing capacitance is sensed to determine the presence of a fingerprint ridge or valley at the particular pixel location. A plurality of pixels arranged in a matrix thus provide a complete image of the fingerprint.
In the construction of a fringing capacitor, touch-sensitive chip, a dielectric layer 12 is deposited over the silicon wafer or substrate 14. An interconnect metal 16 is deposited over the dielectric layer 12 and patterned to provide interconnections between circuits formed in the silicon material of the substrate 14. At this point, the device structure is planarized by depositing a material 18 over the patterned metal 16 and planarizing the material 18. One or more intermediate layers 20 and 22 may be formed over the planarized surface of the device. The metal network 10 forming the plates of the fringing capacitors is formed on the intermediate layers 20 and 22, and again planarized using a material 24, such as a conventional FOX spin-on glass, or other suitable material.
In order to provide a mechanical and chemical protective coating over the surface of the touch-sensitive portion of the chip, it is a conventional practice to form one or more passivation layers of a hard and chemically resistant material, such as silicon nitride 26 and/or silicon carbide 28. In many instances, even when a silicon carbide passivation layer is employed, an underlying silicon nitride layer is also used, as it is well accepted in the industry for its excellent passivation properties. In other words, when the passivation of a new chip constitutes at least some silicon nitride, the chips are more readily accepted and qualified according to conventional semiconductor processing standards. Semiconductor industry standards recognize that silicon nitride is excellent in providing a barrier to ionic diffusion and moisture ingestion. While these passivation materials are well suited for standard semiconductor chips, such materials have many of the shortcomings noted above.
The selection of a passivation material for a semiconductor chip that requires an environmental interface is important, insofar as the dielectric constant is concerned. This is especially the case when touch-sensitive chips are concerned. In this type of chip, perturbations in the capacitive electric field are sensed to determine the contour of the object touching the physical interface of the chip. The electric field between the object touching the chip and the underlaying fringing capacitor network is a function of the dielectric constant of the material layers therebetween. As a result, it has been found that passivation layers are better suited for touch-sensitive chips, when such layer(s) have a relatively low dielectric constant. It is well known that the inorganic silicon-based passivation materials, such as silicon nitride, have a relatively high dielectric constant in the range of about 8-9. Silicon carbide has a dielectric constant of about 9.7. Other dielectric materials, such as the organic family of the polyimide materials, have a relative high dielectric constant in the range of about 3-8.
An important consideration in the design of a physical interface for touch-sensitive chips, is that of xe2x80x9cghostingxe2x80x9d. The properties of the material selected for the physical interface may exacerbate ghosting, where the oils and/or water of previous finger prints remain after the finger is removed. These residues can produce a latent image to the chip even when there is no finger present. This creates problems with security equipment and may interfere with the correct recognition of a current finger print image.
In selecting the type of material for use as a passivation layer for touch-sensitive chips, the thickness of the passivation layer(s) is also a consideration. While thick layers provide a better barrier to chemical invasion and mechanical shock, the sensitivity of the capacitive reaction between the object and the fringing capacitive network is reduced when the passivation layer is thicker. Hence, for optimum performance of a touch-sensitive, fringing capacitive chip, the passivation layer should be highly rugged and resistant to impact shock and scratches, provide a barrier to chemical invasion, be hydrophobic and oleophobic, have a relatively low dielectric constant, and be able to be deposited on the chip surface as a thin layer.
An organic fluoropolymer has recently been developed for use with semiconductor chips. The polymer is disclosed in U.S. Pat. Nos. 4,977,297 and 4,982,056 by Squire, and issued to E. I. du Pont de Nemours and Company (xe2x80x9cDuPontxe2x80x9d). This material has a low dielectric constant of about 2.1, making it well adapted for use with electrical and electronic applications, such as between circuit layers in multi-layer circuit boards. In the Squire patents, the polymer is also indicated as being useful for coating and encapsulating electronic circuits using a solution coating process.
A Teflon(copyright) amorphous fluoropolymer (Teflon AF) is available for use with semiconductor circuits. The Teflon AF has a dielectric constant of 1.89-1.93, and thus makes it a good candidate for use as passivation layers and for encapsulation of hybrid/sandwich integrated circuit packaging. The Teflon AF material can be applied in thin coatings, to the micron level. Teflon(copyright) is DuPont""s registered trademark for fluorinated ethylene propylene, and is used in connection with a variety of low-friction, highly durable products.
It can be seen from the foregoing that a need exists for a physical interface on integrated circuits, where the physical interface is rugged, durable and less susceptible to breakage when subjected to point contact loading, and the like. Another need exists for a single thin physical layer on integrated circuits that can replace the traditional silicon nitride and silicon carbide layers, thereby increasing the sensitivity of the sensing circuits. Yet another need exists for an organic passivation layer that is rugged but somewhat compliant, thereby reducing the tendency of the physical interface to break or crack. A need exists for a physical interface to an integrated chip, where the physical interface reduces latency effects and hypersensitivity to moisture, oils, etc.
The present invention disclosed and claimed herein, in one aspect thereof, comprises a method of passivating an integrated circuit of the type having a physical interface to the environment. In accordance with the principles and concepts of the invention, the method includes the step of depositing a fluorocarbon polymer as an outer layer of the physical interface. This type of physical interface can be applied to the integrated chip as a thin layer that is tough, compliant, and exhibits a low coefficient of friction so that it is resistant to abrasion, scratches and other forms of mechanical damage. The low dielectric constant characteristics of the fluorocarbon polymer make it well adapted for use in fringing capacitive type biometric sensors.
When a fluorocarbon polymer is used as the physical interface to a touch-sensitive chip, the latency of the residual image (once the finger is removed) is substantially reduced.
In another form of the invention, the fluorocarbon polymer can be deposited on the outer surface of the integrated circuit as a passivation layer, in lieu of the conventional silicon nitride and silicon carbide passivation layers. For ease of operation, the fluorocarbon polymer can be applied by spray techniques over the active circuits of the semiconductor device, in the window area of the encapsulation to provide the physical interface to the environment.
In another aspect of the invention, the conventional planarizing and overlying passivation layers of an integrated circuit can be replaced with an organic layer of fluorocarbon polymer which can be planarized, and which also functions as a passivation layer for the chip. In addition, a gettering agent can be implanted in the fluorocarbon polymer material to immobilize deleterious ions, such sodium ions.
In yet another aspect of the invention, particles can be implanted into the surface of the fluorocarbon polymer to produce variations in the electrostatic field generated by the fringing capacitors of a touch-sensitive integrated circuit. Based on the type of particles, the concentration, and the location thereof, such particles can influence the shape and intensity of the electric field in a desired manner.